ASAHI KASEI. [AKD].. / – 7 -. [ADC Plot: fs=48kHz]. AKM. AK THD+N vs. Input Level. VA=VD=V, fs=48kHz, fin=1kHz. AKM Semiconductor AKET. Explore Integrated Circuits (ICs) on Octopart: the fastest AKET. Dual Channel Dual ADC Delta-Sigma 96ksps bit. The AK achieves high accuracy and low cost by using Enhanced dual bit ∆Σ WARNING: AKM assumes no responsibility for the usage beyond the.
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An electrolytic capacitor 2. All voltages with respect to ground.
Alternatively if VA and VD are supplied separately, the power up sequence is not critical. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. The audio interface supports both master and slave modes.
Resolution 24 Bits Input Voltage Note 4 2. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. The AK samples the analog inputs at 64fs. Input voltage is proportional to VA voltage. This reset should always be done after power-up. The AK requires no external components because the analog inputs are single-ended.
Grounding and Power Supply Decoupling The AK requires careful attention to power supply and grounding arrangements.
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If these clocks are not provided, the AK may draw excess current due to its use of internal dynamically refreshed logic. This value is the full scale 0dB of the input voltage. Normal operation is not guaranteed at these extremes. AKM sales office or authorized distributor concerning their current status.
Decoupling capacitors should be as near to the AK as possible, with the small value ceramic capacitor being the nearest.
The input signal range scales with the supply voltage and nominally 0. AKM assumes no responsibility for the usage beyond the conditions in this datasheet.
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The reference frequency of these responses is 1kHz. All digital input pins should not be left floating. Operation at or beyond these limits ak, result in permanent damage to the device. Lead frame surface treatment: An analog initialization cycle starts after exiting the power-down mode.
The ADC outputs settle in the data corresponding to the input signals after the end of initialization Settling approximately takes the group delay time. The calculated delay time induced by digital filtering.
A critical component is one whose failure to function or perform may reasonably be expected 5318 result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Date Code Marketing Code: The passband and stopband frequencies scale with fs.
A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, 5831 other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. In slave mode, the internal timing starts clocking by the rising edge falling edge at mode 1 of LRCK after akkm from reset and power down state by MCLK.
This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC.
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Voltage Reference The voltage input to VA sets the analog input range. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK The digital filter rejects noise above the stop band except for multiples of 64fs.
Before considering any use or application, consult the Asahi Kasei Microsystems Co. The cut-off frequency of the HPF is 1. No load current may be drawn from these pins.
The AK includes an anti-aliasing filter RC filter to attenuate a noise around 64fs. VA and VD are usually supplied from akj analog supply in the system. An evaluation board is available which demonstrates application circuits, the optimum layout, power supply arrangements and measurement results. The power up sequence between VA and VD is not critical. In master mode, the internal timing starts when MCLK is input.